Design Verification (DV) Engineer
Job Description:We are looking for a skilled Design Verification (DV) Engineer with strong expertise in SoC/IP verification. The candidate should have hands-on experience in SystemVerilog, UVM methodology, and protocol-based verification to ensure high-quality RTL designs. Key Responsibilities:* Develop and execute verification plans based on design specifications.* Create and maintain SystemVerilog/UVM-based testbenches.* Develop reusable verification components such as agents, drivers, monitors, and scoreboards.* Perform […]